» Educational Qualifications

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» Publications

SCI-SSCI or SCI Expanded Articles

  • O. Erdem “Pipelined Hierarchical Architecture for High Performance Packet Classiffication” Elsevier Computer Networks vol.103, pp.143-164, April 2016. DOI: 10.1016/j.comnet.2016.04.009 (April 2016)
  • O. Erdem “Tree-based string pattern matching on FPGAs” Elsevier Computers & Electrical Engineering vol.49, pp.117-133, January 2016. DOI: 10.1016/j.compeleceng.2015.11.025 (January 2016)
  • O. Erdem and A.Carus “Multi-Pipelined and Memory-Efficient Packet Classification Engines on FPGAs” Elsevier Computer Communications vol.67, pp.75-91, August 2015. DOI: 10.1016/j.comcom.2015.05.017 (August 2015)
  • O. Erdem, A.Carus and H.Le “Value-Coded Trie Structure for High Performance IPv6 Lookup” The Computer Journal vol.58, no.2, pp.204-214, February 2015. (February 2015)
  • O. Erdem, A.Carus and H.Le “Large-scale SRAM-based IP lookup architectures using compact trie search structures” Elsevier Computers & Electrical Engineering, vol.40, no.4, pp.1186-1198, May 2014. (May 2014)
  • O. Erdem, and C.F. Bazlamaçcı, “High Performance IP Lookup Engine with Compact Clustered Trie Search” IEEE The Computer Journal vol. 55, no.12, pp. 1447-1466, August 2012. (August 2012)
  • O. Erdem and C.F. Bazlamaçcı, “Array design for trie-based IP Lookup” IEEE Communications Letters, vol.14, no.8, pp.773-775, August 2010. (August 2010)

International Conference Proceedings

  • T.Soylu, O. Erdem, A. Carus, E.S.Güner , ”Simple CART Based Real-Time Traffic Classification Engine on FPGAs ” (Accepted) 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17) ,December 2017, Cancun, Mexico. (December 2017)
  • N.T.Kucun, O.Erdem and Y. Yoruk , ”Women Entrepreneurship in Research and Development ” 2014 International Women and Business Conference, pp.24,October 2014, Belgrade, Serbia. (October 2014)
  • O. Erdem and A. Carus , ”Range Tree-Linked List Hierarchical Search Structure for Packet Classification on FPGAs ” 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig'13), pp.1-6,December 2013, Cancun, Mexico. (December 2013)
  • O. Erdem and A. Carus "Clustered Linked List Forest for IPv6 Lookup" 21st Annual Symposium on High-Performance Interconnects (HOTI 2013), pp.33-40, August 2013, Cisco Headquarters, San Jose, San Francisco, CA, USA (August 2013)
  • O. Erdem, A. Carus and H. Le, ”Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs ” 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig'12), pp.1-6,December 2012, Cancun, Mexico. (December 2012)
  • O. Erdem, H. Le and V. K. Prasanna, ”Hierarchical hybrid search structure for high performance packet classification”31st Annual Joint Conference of the IEEE Computer and Communications Societies(INFOCOM’12), pp.1898-1906,March 2012, Orlando, Florida, USA. (March 2012)
  • Y.H. E. Yang, O. Erdem and V. K. Prasanna, " Scalable Architecture for 135 Gbps IPv6 Lookup on FPGA" 19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’12), pp.272-272, February 2012, Monterey, California, USA. (February 2012)
  • O. Erdem, H. Le, V. K. Prasanna and C.F. Bazlamaçcı, "Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs," In Proc. of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’11), pp.95-102, September 2011, Santa Monica, California, USA. (September 2011)
  • O. Erdem, H. Le, and V. K. Prasanna, "Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA" In Proc. of the 21st International Conference on Field Programmable Logic and Applications (FPL’11), pp.201-206, September 2011,Chania, Crete, Greece. (September 2011)
  • Y.H. E. Yang., O. Erdem and V. K. Prasanna, "High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search" In Proc. of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’11), pp.77-80, May 2011,Salt Lake City, Utah, USA. (May 2011)
  • O. Erdem, H. Le, V. K. Prasanna and C.F. Bazlamaçcı, "Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs" In Proc. of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’11), pp.253, May 2011,Salt Lake City, Utah, USA. (May 2011)
  • O. Erdem and C.F. Bazlamaçcı, “MIPS extension for a TCAM based parallel architecture for fast IP lookup” In Proc. of the 24th International Symposium on Computer and Information Sciences (ISCIS'09), pp. 310-315, September 2009, Guzelyurt, Cyprus. (September 2009)

National Conference Proceedings

  • O. Erdem and C.F. Bazlamaçcı, “SRAM based systolic array architecture for fast IP lookup” In Proc. of the 13th Nat. Conference Electrical, Electronics, Computer and Biomedical Engineering Conference, December 2009. (December 2009)

Master`s Theses Advised

  • (Co-supervisor) "TRIE-TREE DATA STRUCTURE FOR IP LOOKUP IN VIRTUAL ROUTERS" Dilek Baysal, Electrical and Electronics Engineering, Middle East Technical University (January 2014)
  • (Co-supervisor) "MEMORY ORGANIZATION IN PIPELINED HIERARCHICAL SEARCH STRUCTURES FOR PACKET CLASSIFICATION" Cağla Irmak Rumelili, Electrical and Electronics Engineering, Middle East Technical University (June 2013)

Memberships

  • 2013 International Conference on ReConFigurable Computing and FPGAs (Reconfig 2013) Program Committee Member (June 2013)

Referee Positions

  • ETRI Journal (January 2014)
  • Journal of Computer Science and Technology (JCST) (January 2012)
  • Transactions on Parallel and Distributed Systems (TPDS) (January 2011)

Awards

  • Best Doctorate Thesis of 2011 in METU (April 2011)

Other

  • Bazlamaçcı, C.F. and Erdem, O. “Systolic array architecture for fast IP lookup”, US Patent No: US 8,724624 B, Date of patent: May 13, 2014 (May 2014)
  • Bazlamaçcı, C.F. and Erdem, O. “Systolic array architecture for fast IP lookup”, Japanese Patent No: 5529976, Date of patent: April 25, 2014 (April 2014)
  • Bazlamaçcı, C.F. and Erdem, O. “Systolic array architecture for fast IP lookup”, European Patent No: EP2517420B1, Date of patent: March 19, 2014 (March 2014)

» Courses Given

Algorithms and Programming

Introduction to Computers

Logic Circuits

Microprocessors